1. Field
The present technology relates to high density memory devices, such as memory devices in which multiple levels of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
In one trend to achieve high density memory, designers have been looking to techniques for stacking multiple levels of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
More recently, advanced 3D technologies developed have been described in U.S. Patent Application Publication No. US 2012/0007167, published 12 Jan. 2012, and filed 31 Jan. 2011, entitled 3D MEMORY ARRAY WITH IMPROVED SSL AND BL CONTACT LAYOUT, in U.S. Patent Application Publication No. US 2012/0007167, published 12 Jan. 2012, and filed 31 Jan. 2011, entitled ARCHITECTURE FOR A 3D MEMORY ARRAY, and in U.S. patent application Ser. No. 13/772,058, filed 20 Feb. 2013, entitled 3D NAND FLASH MEMORY.
It is desirable to provide technologies can improve program and erase performance in high density memory.